ICs can include an array of DRAM cells. The memory cells comprise a storage node which carries a charge that represents the stored information. Due to parasitic leakage paths, the charge stored within the storage node decreases. The charge must be refreshed at least once during the retention time. The retention time is set such that the storage node has always enough charge so that it can be detected by a sense amplifier. During a refresh cycle, the information stored in the memory cells of a row is read out, amplified, and written back into the memory cells of that row.
In conventional ICs, when an array is refreshed, the memory array is prevented from read or write accesses. Accesses are permitted only after the refresh operation is completed. The necessity of refresh operation hinders the performance of the memory array.
From the foregoing discussion, it is desirable to provide memory arrays which reduces the performance degradation associated with refresh operations.
The invention relates generally to improving performance of memory accesses in ICs with memory cells. In one embodiment, an IC comprises an array of memory cells arranged in rows and columns. A row includes a plurality of words in which a word comprises x memory cells, where x is greater than or equal to 1. During a memory access cycle, one of the words in a selected row is accessed. At least one other word in the selected row is refreshed during the same memory access cycle. Preferably some of the other words in the selected row are refreshed during the same memory access cycle, and more preferably the other words in the selected row are refreshed during the same memory cycle.